1. Field of the Invention
The present invention relates to a ESD protection device design for semiconductor devices and, more particularly, to form ESD protective device by using an ion implant without additional photo mask.
2. Description of the Prior Art
With the popularity of the device features scaling down in the integrate circuit manufacturing, some of the problems such as hot carrier effect, punchthrough effect become stringent challenges. In addition, there are electrostatic discharge issues will be suffered. Since the gate oxide thickness of the MOS devices is decreased with the advance of the IC's technique. The thinner the gate oxide formed, the greater susceptibility for these devices come to damage from the excessive voltages such as caused by an electrostatic discharge (ESD) event. During an ESD event, charges are transferred from one or more pins of the integrated circuits into devices in a very short duration, typically less than one microsecond. The transfer charges generates voltages that are large enough to break down insulating films, e.g., gate oxides on MOSFET devices, or that can dissipate sufficient energy to cause thermal failures in the devices. Consequently, in order to overcome aforementioned problems, it is important to form ESD protective devices during manufacturing the functional devices.
Take the dynamic random access memories (DRAM) or static random access memories (SRAM) as an example, to improve the fabricated technology so as to increase the integrity per unit chip area and promote the competitive ability are a common target of the industries. Thus the tightly layout between the shallow trench isolation and the active region has become. For instance, FIG. 1 shows a MOSFET from the bottom to the up having a stack gate structure of gate oxide 10A, a polysilicon layer 10B, a tungsten silicide 10C and silicon nitride cap layer 10D, and a silicon nitride spacer 10E formed on the substrate 5. A silicon nitride liner layer 15 and an interlevel dielectric layer 30 are then atop the stack gate and all remaining areas. The silicon nitride liner layer 15 is to prevent the oxide layer in the shallow trench isolation 18 from the overetch during the source/drain 10F contact formation process. Since the active region (the source/drain region 10F) having the width is almost the same as the contact size so as to fully utilize the planar area and minimize the contact resistance. As a result, to avoid the overlay error during lithographic process, the silicon nitride liner 15 acts as an etching stop layer and the silicon nitride spacer 10E as the barrier of short between gate and the source/drain during contact formation. Because the cap layer 10D of about 1000 A compared to 300-400 A in thickness of the silicon nitride liner layer 15, another photoresist pattern define the gate contact is generally necessary. The results are shown in FIG. 1B.
As forgoing processes, as depicted before, a number of ESD protective transistors will be formed at the periphery of each die. The ESD protective transistors may form during DRAM or SRAM transistor device fabricate simultaneously or using extra processes to form in accordance with the process difference. However, the process difference, the extra lithographic process is generally demanded.
Thus, an object of the present invention is intended to provide a method to form the ESD protective transistor without additional lithographic process so as to reduce the cycle time and the cost.